Dr. Yung-Ting Hsieh
Timeline
2022, 2025-Present
TE Connectivity
Sr. R&D Product/Development Engineer
Started as a Signal Integrity Electrical Engineering Intern in 2022 and returned as a full-time Sr. R&D Product/Development Engineer, building AI-assisted SI modeling workflows and leading high-speed interconnect development through simulation, measurement correlation, and product-facing execution.
Sr. R&D Product/Development Engineer
Physics-Based SI × AI-Enhanced R&D
Education
Ph.D.
Rutgers University
Top 40 U.S.
MS
National Chiao Tung University
Top 3 Taiwan
BS
National Chung Hsing University
Top 6 Taiwan
HS
Tainan First Senior High School
Top 3% Selective
HS
Tainan First Senior High School
Top 3% Selective
BS
National Chung Hsing University
Top 6 Taiwan
MS
National Chiao Tung University
Top 3 Taiwan
Ph.D.
Rutgers University
Top 40 U.S.
Sr. R&D Product/Development Engineer at TE Connectivity with 4+ years of advanced Signal Integrity expertise and 7+ years of AI/ML development experience. Focused on circuit modeling, engineering AI workflows, and system-level problem solving.
Software
Hardware
Developing AI for advanced SI parameter prediction: 4000x faster iterations, ~4% prediction error, and ~$12.5M estimated savings.
Timeline
2022, 2025-Present
TE Connectivity
Sr. R&D Product/Development Engineer
Started as a Signal Integrity Electrical Engineering Intern in 2022 and returned as a full-time Sr. R&D Product/Development Engineer, building AI-assisted SI modeling workflows and leading high-speed interconnect development through simulation, measurement correlation, and product-facing execution.